/Nano4kAudio

This is a brute-force attempt to port https://github.com/hdl-util to the Tang Nano 4k FPGA board including the audio feature. The original code makes use of several system verilog features not fully supported by the Gowin IDE. Clock generation and IO serialization require device specific handling. The final goal is a pull request to the original project with conditional defines to support the Gowin FPGA and the Tang Nano 4k board.

Primary LanguageSystemVerilogOtherNOASSERTION

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