PyFive-RISC-V

caravel_pyfive

circuitpython

CircuitPython - a Python implementation for teaching coding with microcontrollers

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

pyfive

PyFive - RISC-V libre silicon microcontroller design leveraging the new Google/SkyWater 130nm PDK

pyfive-mpw1-pcb

Breakout carrier for the MPW1 PyFive chip

pyfive-mpw1-postmortem

pyfive-spi

SPI peripheral for Pyfive

pyfive_no2usb

OpenLane design for the no2usb core

pyfive_top_202011

Top level for the November shuttle

VexRiscv-netlist

PyFive-RISC-V/pyfive_top_202011

Top level for the November shuttle

PyFive-RISC-V/caravel_pyfive

PyFive-RISC-V/pyfive

PyFive - RISC-V libre silicon microcontroller design leveraging the new Google/SkyWater 130nm PDK

PyFive-RISC-V/pyfive_no2usb

OpenLane design for the no2usb core

PyFive-RISC-V/circuitpython

CircuitPython - a Python implementation for teaching coding with microcontrollers

PyFive-RISC-V/pyfive-mpw1-pcb

Breakout carrier for the MPW1 PyFive chip

PyFive-RISC-V/pyfive-spi

SPI peripheral for Pyfive

PyFive-RISC-V/pyfive-mpw1-postmortem

PyFive-RISC-V/open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

PyFive-RISC-V/openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

PyFive-RISC-V/VexRiscv-netlist

PyFive-RISC-V/magic

Magic VLSI Layout Tool

PyFive-RISC-V/openlane-baremetal

PyFive-RISC-V/pyfive-risc-v.github.io

Pyfive Docs

PyFive-RISC-V/skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.