RESMIRNAIR

Pinned Repositories

4BIT_RIPPLECOUNTER
Language:Verilog149
BCD_7SEGMENT
Language:Verilog170
DIGI_LOCK
Language:Verilog130
ELEVATOR_CONTROL
Language:Verilog128
FULL_SUBTRACTOR
Language:Verilog176
JK_FLIPFLOP
Language:Verilog152
MEALY_1101
Language:Verilog133
MOORE_1011
Language:Verilog137
SR_FLIPFLOP
Language:Verilog147
4BIT_SYNCHRONOUS_UP_COUNTER
Language:C056

RESMIRNAIR's Repositories

RESMIRNAIR/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools
Experiment -2
RESMIRNAIR/study-of-basic-gates
Language:VHDL
RESMIRNAIR/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool
Academic Cadence Experiments
RESMIRNAIR/HALF_ADDER
Language:C90
RESMIRNAIR/8BIT_SYNCHRONOUS_UP-DOWN_COUNTER
Language:C40
RESMIRNAIR/PRIORITY_ENCODER
Language:C54
RESMIRNAIR/BCD_7SEGMENT
Language:Verilog170
RESMIRNAIR/RIPPLECARRYADDER
Language:C50
RESMIRNAIR/FULL_SUBTRACTOR
Language:Verilog176
RESMIRNAIR/HALF_SUBTRACTOR
Language:C70
RESMIRNAIR/VLSI-LAB-EXP-1
Language:Verilog1
RESMIRNAIR/FULL_ADDER
Language:C78
RESMIRNAIR/half
RESMIRNAIR/halfadder1
RESMIRNAIR/4BIT_SYNCHRONOUS_UP_COUNTER
Language:C56
RESMIRNAIR/SISO_SR
Language:C25
RESMIRNAIR/PISO_SR
Language:C29
RESMIRNAIR/DIGI_LOCK
Language:Verilog130
RESMIRNAIR/MEALY_1101
Language:Verilog133
RESMIRNAIR/MOORE_1011
Language:Verilog137
RESMIRNAIR/ALU
Language:Verilog62
RESMIRNAIR/4BIT_RIPPLECOUNTER
Language:Verilog149
RESMIRNAIR/JK_FLIPFLOP
Language:Verilog152
RESMIRNAIR/SR_FLIPFLOP
Language:Verilog147
RESMIRNAIR/T_FLIPFLOP
Language:C45
RESMIRNAIR/D_FLIPFLOP
Language:C47
RESMIRNAIR/DEMULTIPLEXER1TO4
Language:C52
RESMIRNAIR/ENCODER8TO3
Language:C74
RESMIRNAIR/Multiplexer4to1
Language:C63
RESMIRNAIR/DECODER2TO4
Language:C74