/neorv32-pynq-z1

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Primary LanguageVHDLBSD 3-Clause "New" or "Revised" LicenseBSD-3-Clause

NEORV32

The NEORV32 RISC-V Processor

datasheet (pdf) datasheet (html) userguide (pdf) userguide (html) doxygen

  1. Overview
  2. Features
  3. FPGA Implementation Results
  4. Performance
  5. Software Framework & Tooling
  6. Getting Started 🚀

1. Overview

neorv32 Overview

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) built around the NEORV32 RISC-V CPU and written in platform-independent VHDL. The processor is intended as auxiliary controller in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus low-power & low-density FPGA. The project is intended to work out of the box and targets FPGA / RISC-V beginners as well as advanced users.

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory accesses are properly acknowledged and that all invalid/malformed instructions are always detected as such. Whenever an unexpected situation occurs the application software is informed via precise and resumable hardware exceptions.

Want to know more? Check out the project's rationale.

💡 Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.

Key Features

  • all-in-one package: CPU + SoC + Software Framework & Tooling
  • completely described in behavioral, platform-independent VHDL - no platform-specific primitives, macros, attributes, etc.; an all-Verilog "version" is also available
  • extensive configuration options for adapting the processor to the requirements of the application
  • highly extensible hardware - on CPU, processor and system level
  • aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
  • FPGA friendly (e.g. all internal memories can be mapped to block RAM - including the CPU's register file)
  • optimized for high clock frequencies to ease integration / timing closure
  • from zero to "hello world!" - completely open source and documented
  • easy to use even for FPGA / RISC-V starters – intended to work out of the box

Project Status

release commits-since-latest-release

Task Repository CI Status
GitHub Pages (docs) neorv32 GitHub Pages
Build documentation neorv32 Documentation
Processor (SoC) verification neorv32 Processor
RISCOF core verification neorv32-riscof neorv32-riscof
FPGA implementations neorv32-setups Implementation
All-Verilog "version" neorv32-verilog neorv32-verilog
Prebuilt GCC toolchains riscv-gcc-prebuilt Prebuilt_Toolchains

The processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the neorv32-riscof repository. It can successfully run any C program (for example from the sw/example folder) including CoreMark and FreeRTOS and can be synthesized for any target technology - tested on Intel, Xilinx and Lattice FPGAs. The conversion into a plain-Verilog netlist module is automatically checked by the neorv32-verilog repository.

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2. Features

The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. By using generics the design is highly configurable and allows a flexible customization to tailor the setup according to your needs. Note that all of the following SoC modules are entirely optional.

CPU Core

  • NEORV32_MARCHID - see the open-source architecture ID list in the official RISC-V ISA manual repository
  • 32-bit little-endian RISC-V single-core, pipelined/multi-cycle modified Harvard architecture
  • configurable ISA extensions:
    RV32 [I/ E] [M] [A] [C] [B] [U] [X] [Zicntr] [Zicsr] [Zicond] [Zihpm] [Zifencei] [Zfinx] [Zmmul] [Zxcfu] [PMP] [Sdext] [Sdtrig]
  • compatible to subsets of the RISC-V Unprivileged ISA Specification (pdf) and Privileged Architecture Specification (pdf).
  • machine and user privilege modes
  • implements all standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension
  • custom functions unit (CFU as Zxcfu ISA extension) for custom RISC-V instructions (R3-type, R4-type and R5-type);
  • intrinsic libraries for CPU extensions that are not yet supported by GCC

Memories

  • processor-internal data and instruction memories (DMEM / IMEM) & caches (iCACHE and dCACHE)
  • pre-installed bootloader (BOOTLDROM) with serial user interface; allows booting application code via UART or from external SPI flash

Timers and Counters

  • 64-bit machine system timer (MTIME), RISC-V spec. compatible
  • 32-bit general purpose timer (GPTMR)
  • watchdog timer (WDT)

Input / Output

SoC Connectivity

  • 32-bit external bus interface - Wishbone b4 compatible (WISHBONE); wrappers for AXI4-Lite and Avalon-MM host interfaces
  • stream link interface with independent RX and TX channels - AXI4-Stream compatible (SLINK)
  • external interrupts controller with up to 32 channels (XIRQ)

Advanced

  • true random number generator (TRNG) based on the neoTRNG
  • execute-in-place module (XIP) to execute code right from a SPI flash
  • custom functions subsystem (CFS) for custom tightly-coupled co-processors, accelerators or interfaces
  • direct memory access controller (DMA) for CPU-independent data transfers and conversions
  • cyclic redundancy check unit (DMA) to test data integrity (CRC8/16/32)

Debugging

  • on-chip debugger (OCD) accessible via standard JTAG interface
  • compliant to the "Minimal RISC-V Debug Specification Version 1.0"
  • compatible with OpenOCD + gdb and Segger Embedded Studio

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3. FPGA Implementation Results

Implementation results for exemplary CPU configurations generated for an Intel Cyclone IV EP4CE22F17C6 FPGA using Intel Quartus Prime Lite 21.1 (no timing constrains, balanced optimization, f_max from Slow 1200mV 0C Model).

CPU Configuration (version 1.7.8.5) LEs FFs Memory bits DSPs f_max
rv32i_Zicsr 1223 607 1024 0 130 MHz
rv32i_Zicsr_Zicntr 1578 773 1024 0 130 MHz
rv32imc_Zicsr_Zicntr 2338 992 1024 0 130 MHz

Implementation results for an exemplary SoC/Processor configurations generated for a Xilinx Artix-7 xc7a35ticsg324-1L FPGA using Xilinx Vivado 2019.2 (no constraints except for clock speed).

SoC Configuration (version 1.7.7.3) LUTs FFs BRAMs DSPs Clock
CPU: rv32imcu_Zicsr_Zicnt_DEBUG + FST_MUL + FAST_SHIFT; Peripherals: UART0 + MTIME + GPIO 2488 1807 7 4 150 MHz

💡 An incremental list of the CPU extensions and the Processor modules can be found in the Data Sheet: FPGA Implementation Results.

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4. Performance

The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available CPU extensions.

The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing 2000 iterations of the CoreMark CPU benchmark (using plain GCC10 rv32i built-in libraries only!).

CPU Configuration (version 1.5.7.10) CoreMark Score CoreMarks/MHz Average CPI
small (rv32i_Zicsr) 33.89 0.3389 4.04
medium (rv32imc_Zicsr) 62.50 0.6250 5.34
performance (rv32imc_Zicsr + perf. options) 95.23 0.9523 3.54

💡 More information regarding the CPU performance can be found in the Data Sheet: CPU Performance. The CPU & SoC provide further "tuning" options to optimize the design for maximum performance, maximum clock speed, minimal area or minimal power consumption: UG: Application-Specific Processor Configuration

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5. Software Framework and Tooling

  • core libraries for high-level usage of the provided functions and peripherals
  • application compilation based on GNU makefiles
  • gcc-based toolchain (pre-compiled toolchains available)
  • SVD file for advanced debugging and IDE integration
  • bootloader with UART interface console
  • runtime environment for handling traps
  • several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
  • doxygen-based documentation, available on GitHub pages
  • supports implementation using open source toolchains - both, software and hardware can be developed and debugged with open source tools (GHDL, Yosys, nextpnr, openOCD, gtkwave, ...)
  • continuous integration is available for:
    • allowing users to see the expected execution/output of the tools
    • ensuring RISC-V specification compatibility using RISCOF
    • catching regressions
    • providing ready-to-use and up-to-date bitstreams and documentation

💡 Want to know more? Check out the Data Sheet: Software Framework.

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6. Getting Started

This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.

🔍 Project Overview

🔌 Hardware Overview

💾 Software Overview

🚀 User Guide

©️ Legal

license DOI

  • Overview - license, disclaimer, limitation of liability for external links, proprietary notice, etc.
  • Citing - citing information

This is an open-source project that is free of charge. Use this project in any way you like (as long as it complies to the permissive license). Please cite it appropriately. 👍

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❤️ A big shout-out to the community and all the contributors, who helped improving this project!