RIOSMPW
The RISC-V International Open Source Laboratory (RIOS Lab) will bring the research effort of RISC-V CPU ecosystems from UC Berkeley to the rest of the world
Pinned Repositories
CyberRio-V1.0
A small RISC-V core written in synthesizable Verilog, with the majority of the Verilog code implementation done using GPT-4, that supports the RV32I unprivileged ISA and parts of the privileged ISA, namely M-mode.
GreenRio-V1.0
Open source RISC-V CPU
GreenRio-V2.0
Open source RISC-V CPU
Open3DFlow
An open-source 3D IC design platform that leverages existing open EDA tools while incorporating tailored abstractions and customizations optimized for 3D chiplet designs.
OpenBMIChip
The OpenBMIChip is an incredible piece of silicon chip, specifically designed to support the incredibly fascinating Brain-Machine Interface (BMI).
OpenRPDK28
Open source process design kit for 28nm open process
OpenSTDCell28
Open stadard cell library for open 28nm process
OpenXRAM
sram/rram/mram.. compiler
sail-rgen
Sail architecture definition language with RGen enhancements
sail-riscv-rgen
Sail RISC-V model with RGen enhancements
RIOSMPW's Repositories
RIOSMPW/OpenRPDK28
Open source process design kit for 28nm open process
RIOSMPW/OpenXRAM
sram/rram/mram.. compiler
RIOSMPW/CyberRio-V1.0
A small RISC-V core written in synthesizable Verilog, with the majority of the Verilog code implementation done using GPT-4, that supports the RV32I unprivileged ISA and parts of the privileged ISA, namely M-mode.
RIOSMPW/Open3DFlow
An open-source 3D IC design platform that leverages existing open EDA tools while incorporating tailored abstractions and customizations optimized for 3D chiplet designs.
RIOSMPW/OpenSTDCell28
Open stadard cell library for open 28nm process
RIOSMPW/sail-rgen
Sail architecture definition language with RGen enhancements
RIOSMPW/GreenRio-V1.0
Open source RISC-V CPU
RIOSMPW/GreenRio-V2.0
Open source RISC-V CPU
RIOSMPW/OpenBMIChip
The OpenBMIChip is an incredible piece of silicon chip, specifically designed to support the incredibly fascinating Brain-Machine Interface (BMI).
RIOSMPW/sail-riscv-rgen
Sail RISC-V model with RGen enhancements
RIOSMPW/3DChipTech
RIOSMPW/CXLandNUMA
Resource map of CXL, NUMA and UCIe
RIOSMPW/OpenChatEDA
Large language model platform for EDA tool
RIOSMPW/PicoRioCPU2641300
PicoRio2 CPU MPW
RIOSMPW/RIOSMPW