RISC-KC

Pinned Repositories

basic_rv32s
🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.
Language:Verilog61
ima_make_rv64
I'ma make rv64 cpu.
10

RISC-KC's Repositories

RISC-KC/basic_rv32s
🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.
Language:Verilog61
RISC-KC/ima_make_rv64
I'ma make rv64 cpu.
1