RapidSilicon

CFU-comefa

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

FPGA_Perf_Check

OpenFPGA

An Open-source FPGA IP Generator

qemu-rs

Rapid Silicon fork of the Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

renode-infrastructure_rs

renode-verilator-integration_rs

This repository contains a sample code integrating Renode with Verilator

renode_rs

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

spydrnet-physical-rs

This is a SpyDrNet Plugin for a physical design related transformations

spydrnet-rs

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

vtr-verilog-to-routing_1.5

update for vpr_1.5

RapidSilicon/spydrnet-rs

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

RapidSilicon/OpenFPGA

An Open-source FPGA IP Generator

RapidSilicon/CFU-comefa

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

RapidSilicon/FPGA_Perf_Check

RapidSilicon/qemu-rs

Rapid Silicon fork of the Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

RapidSilicon/renode-infrastructure_rs

RapidSilicon/renode-verilator-integration_rs

This repository contains a sample code integrating Renode with Verilator

RapidSilicon/renode_rs

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

RapidSilicon/spydrnet-physical-rs

This is a SpyDrNet Plugin for a physical design related transformations

RapidSilicon/vtr-verilog-to-routing_1.5

update for vpr_1.5