RaviVijay/DeepLearningEE

Collection of Papers and Trials on Deep Learning to aid EE design

DeepLearningEE

Collection of Papers on Deep Learning to aid EE design

Birds View

Jeff Dean: The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design::ZDNet Article

Survey of DL for Scientific Discovery(2020)

Tech. Report : End-to-End DRL in Computer Systems(2020)

Machine Learning for Engineering(2018)

Thesis: New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design(2016)

Thesis: Low Power EDA(2006)

Data

Metrics

Tools

OpenRoad :: Paper

Park Platform for Reinforcement Learning in Systems

Quantum Circuit Optimization

ChipKit: Agile Open Src Framework

Algorithms

Heuristic Algorithms

Reinforcement Learning + Heuristics(2019)

Graph Algorithms

Understanding Graphs in EDA

Generalized Clustering by Learning to Optimize Expected Normalized Cuts

GAP Partitioning Framework :: Deep Learning Framework for Graph Partitioning(GAP)(2019)

Clustering

Generalized Clustering to Optimize Cuts :::: Code

Simulator Speed Up

Billion Times :: Paper

Circuit Simulation Parallelization

Coping with Envions with Slow Simulator and Fast Approximations

Analog Design

Agent Training Framework For Analog Design

AutoCkt: Deep Reinforcement Learning of AnalogCircuit Designs

Learning to Design Circuits(2018)

Differential Simulator

Placement Quality Prediction using Transfer Learning

Digital Design

Standard Cells

Generating power-optimal std cell lib spec using NN(2017)

DFT

GCN for Testability Analysis

HLS

AutoPhase: Phase Ordering for HLS using DRL(2019)

Synthesis

New Full Adders using MLP(2020)

LSOracle: Synthesis Framework Driven by AI(2019)

DL based Ckt Recognition using sparse mapping(2019)

Deep-PowerX Low Power Approximation Synthesis

Improving SAT Solvers(2019)

Approximate Logic Synth Using Reinforcement Learning(2019)

Perf. Esti of Synth Flows using LSTM & Transfer Learning(2018)

Cadence: A Learning Bridge from Arch. Synthesis to PD for Exploring Power Efficient High-Performance Adders(2017)

Cadence, Intel: Cross-layer Optimization for High Speed Adders:A Pareto Driven Machine Learning Approach(2018)

Power Grid + Integrity

PowerPlanningDL: Reliability-Aware Framework for PGD using DL(2020)

Template-based PDN Synthesis in Floorplan and PlacementUsing Classifier and CNN Techniques(2020)

IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop(2019)

IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design(2019)

Generating Routing Driven Power Distribution n/w using ML Techniques(2017)

PDN Simplifier(2018)

Fast PI Classifier

Floorplan

Solving Packing Problems by Conditional Query Learning(2020)

Routability Driven Macro Placement

Memory Controller Placement(2019)

NOC Component Charecterization

Placement

Chip Placement with DRL

Placement Optimization using DRL

Legalization(2019) Presentation

CTS

Routing

Cadence - Attention Based RL for Track Assign + Detail Routing(2020)

Nvidia's CongestionNet

Deep Reinforcement Learning for Global Routing

Congestion Prediction using GANs

Congestion Prediction using Conditional GANs

Pin Accessibility Prediction

Ckt Routing using Monte Carlo Tree Search and DL

Route Coloring

Coloring: Adaptive Layout Decomposition

DL Driven Decompostion & Mask Optimization

Verification

Deep Predictive Coverage Collection(Nvidia)

STA

Package

Automatically Designed EBG

Reliability

predict vlsi circuit reliability risks using neural network(2014)

Power Analysis

Power Modeling and Estimation Survey 2020

Power Inference

Variation Modeling

Variation Modeling

Automatic tuning of a quantum device

Manufacturing

Defect Prediction in PCBs

Computer Architecture

Resource Mngt

Resource Management of Heterogenous SoCs

DVFS

Data Driven DVFS Schedule for GPU

Literature Survey

Prefetch

Classifying Memory Access patterns for Prefetching

LSTM Based Prefetcher Thesis 2017

Cache Replacement

Imitation Learning for Cache Replacement

Power Modeling

Learning based Power Modelling