/Multi-Cycle-CPU

A implementation of a simple Multi-Cycle CPU in RISC-V instructions

Primary LanguageVerilogMIT LicenseMIT

This is a Multi-Cycle RISC-V CPU implementation

1. Instructions

The CPU is implemented by Verilog. The testcases of the CPU is in the sim_1/new/cpu_test_tb.v.

The memory is a kind of cache. Not the memory. The Instruction Set Architecture is RISC-V.