Pinned Repositories
chisel3
Chisel 3: A Modern Hardware Design Language
Computer-Science-Textbooks
Collect some CS textbooks for learning.
CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++
e200_opensource
The Ultra-Low Power RISC Core
hello-world
Just guidence
Helmet-Detection
This project is a proof-of-concept, trying to show surveillance of roads for the safety of motorcycle and bicycle riders can be done with a surveillance camera and an onboard Jetson platform.
hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
hwacha-template
Template for projects using the Hwacha data-parallel accelerator
LeNet_Cpp_Remake
Simplified LeNet-5 with C++ based on x86 & RISC-V
RicardoYX.github.io
RicardoYX's Repositories
RicardoYX/RicardoYX.github.io
RicardoYX/chisel3
Chisel 3: A Modern Hardware Design Language
RicardoYX/Computer-Science-Textbooks
Collect some CS textbooks for learning.
RicardoYX/CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++
RicardoYX/e200_opensource
The Ultra-Low Power RISC Core
RicardoYX/hello-world
Just guidence
RicardoYX/Helmet-Detection
This project is a proof-of-concept, trying to show surveillance of roads for the safety of motorcycle and bicycle riders can be done with a surveillance camera and an onboard Jetson platform.
RicardoYX/hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
RicardoYX/hwacha-template
Template for projects using the Hwacha data-parallel accelerator
RicardoYX/LeNet_Cpp_Remake
Simplified LeNet-5 with C++ based on x86 & RISC-V
RicardoYX/libpku
北京大学课程资料整理
RicardoYX/liuyanban
RicardoYX/mips-32bit
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board
RicardoYX/my-movies
use angular7 to build a weapp.
RicardoYX/oscpu-framework
A Verilator-based demo.
RicardoYX/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
RicardoYX/PLCT-Open-Reports
PLCT实验室的公开演讲，或者决定公开的组内报告
RicardoYX/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
RicardoYX/riscv-isa-manual
RISC-V Instruction Set Manual
RicardoYX/riscv-isa-sim
Spike, a RISC-V ISA Simulator
RicardoYX/riscv-tools
RISC-V Tools (ISA Simulator and Tests)
RicardoYX/RV32
verilog RV32 cpu (CS3410)
RicardoYX/tutorials
教程
RicardoYX/USTC-CS-Courses-Resource
:heart:**科学技术大学计算机学院课程资源(https://mbinary.xyz/ustc-cs/)
RicardoYX/vortex
RicardoYX/vue_start
IT includes a vue2 webapp and a server writed by node.js
RicardoYX/writing-your-first-riscv-simulator
《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
RicardoYX/XiangShan
Open-source high-performance RISC-V processor
RicardoYX/zero-riscy
zero-riscy CPU Core