/Synchronous-4-bit-ALU

Building an ALU that have the outputs that prints out results at certain cycles using Non-blocking, and shift registers concepts

Primary LanguageVerilog

Synchronous-4-bit-ALU

Building an ALU that have outputs that print out results at certain cycles using Non-blocking and shift registers concepts

#ALU Functional Specifications 4-bit ALU Takes the inputs: Takes Clock, Reset 4-bit input A 4-bit input B 1-bit c_in (or b_in) 4-bit control signal ctrl Produces: 1-bit valid 4-bit output C 1-bit c_out (or b_out) 2-bit compare_out

Control Signal Values -->> Operation to be performed

December 2023: I would begin implementing design verification in this module.