Ritwik-Kaushik

Pinned Repositories

fedar-f1-rv64im
5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
Language:Verilog187 7 319
ardupilot
ArduPlane, ArduCopter, ArduRover, ArduSub source
Language:C++00
ComputerVision
Language:Jupyter Notebook00
Ritwik-Kaushik
Config files for my GitHub profile.
00

Ritwik-Kaushik's Repositories

Ritwik-Kaushik/ardupilot
ArduPlane, ArduCopter, ArduRover, ArduSub source
Language:C++00
Ritwik-Kaushik/ComputerVision
Language:Jupyter Notebook00
Ritwik-Kaushik/Ritwik-Kaushik
Config files for my GitHub profile.
00