Rohan7Gupta/pentaRV
pentaRV consists of a 5 stage pipelined Rv32I core and the project plans to implement a RISC-V based SOC .
VerilogApache-2.0
No issues in this repository yet.
pentaRV consists of a 5 stage pipelined Rv32I core and the project plans to implement a RISC-V based SOC .
VerilogApache-2.0
No issues in this repository yet.