/riscv-zig

A RISC-V emulator written in Zig

Primary LanguageZigMIT LicenseMIT

RV64IM emulator

This repository contains a library for emulating RISC-V 64 CPUs with the multiply extension.

Caveat emptor: The implementation of RISC-V contained herein has not been tested for compliance. It may produce incorrect results, and it most certainly does not reject all invalid instructions.

(C) 2021 Ronsor Labs.

TODO

  • Support RV32 too (should be easy)
  • Implemented privileged instructions
  • Better documentation