Pinned Repositories
ALU-With-Class-Based-TB-SV
A verification environment for an ALU using class-based testbench in `Systemverilog`
APTProject
Async-FIFO
An Asynchronous FIFO Design that contains synchronizers to avoid metastability that may occur due to full and empty flags
Blinking_LED_Control
This project controls a LED that blink through variable PWM signal created by a timer, and defined by the LED driver user.
Circuitd_NA_Solver
Computer-Architecture-Labs
Finalizing-Chip
RSA-Encrypted-Chat
VLSI-Adders-Mania
Wild-Run
Rufaida-Kassem's Repositories
Rufaida-Kassem/RSA-Encrypted-Chat
Rufaida-Kassem/Finalizing-Chip
Rufaida-Kassem/VLSI-Adders-Mania
Rufaida-Kassem/Wild-Run
Rufaida-Kassem/ALU-With-Class-Based-TB-SV
A verification environment for an ALU using class-based testbench in `Systemverilog`
Rufaida-Kassem/APTProject
Rufaida-Kassem/Async-FIFO
An Asynchronous FIFO Design that contains synchronizers to avoid metastability that may occur due to full and empty flags
Rufaida-Kassem/Blinking_LED_Control
This project controls a LED that blink through variable PWM signal created by a timer, and defined by the LED driver user.
Rufaida-Kassem/Circuitd_NA_Solver
Rufaida-Kassem/Computer-Architecture-Labs
Rufaida-Kassem/cs-video-courses
List of Computer Science courses with video lectures.
Rufaida-Kassem/Smart-Elevator
Rufaida-Kassem/Elevator-Controller
An Elevator controller implemented in `VHDL` as an `FPGA` Design Internship GP
Rufaida-Kassem/FPGA-Labs
Rufaida-Kassem/Gesture_Hero
Gesture Hero is a hand gesture classification system that's build to differentiate between hand gestures representing numbers from 0-5.
Rufaida-Kassem/github-slideshow
A robot powered training repository :robot:
Rufaida-Kassem/Logic-Design-CAD
Rufaida-Kassem/Mars-Exploration
Course Name: Data Structures and Algorithms
Rufaida-Kassem/Museum_APP
Rufaida-Kassem/Neural-Networks-Labs
Rufaida-Kassem/OS-Simulator
This is the final project for Operating Systems course which we build a simulator for the OS kernel like process management and memory management.
Rufaida-Kassem/RISC-Processor
Five-stages pipeline processor using verilog
Rufaida-Kassem/Rufaida-Kassem
Rufaida-Kassem/Search-Engine
Rufaida-Kassem/SPI-Implementation
Rufaida-Kassem/statistics