SAFEERHYDER/Digital-System-Design

This repository manages DSD lab code files.

Digital System Design - Teaching Labs - Spring 2021

Department of Electrical Engineering, Sukkur IBA University

Instructor: Safeer Hyder, PhD, University of Leeds, England

Course Description:

The course covers digital design topics such as digital logic, sequential building blocks, finite-state machines, FPGAs, timing and synchronization. The semester begins with lectures and problem sets, to introduce fundamental topics before students embark on lab assignments and ultimately, a digital design project. The course relies on extensive use of Verilog® for describing and implementing digital logic designs on FPGA development board.

Labs' Titles:

1. Verilog HDL Gate-Level Modelling
2. Hierarchical Modelling Approach
3. Introduction to Data Flow Modelling
4. Behavioural Modelling for Combinational Circuits
5. Behavioural Modelling for Sequential Circuits I
6. Behavioural Modelling for Sequential Circuits II
7. Vivado Post-synthesis and Post-implementation timing simulation
8. A 3rd Order Moving Average Filter using Verilog HDL
9. Finite State Machines
10. FIR Low Pass Gaussian Filter

Important Links:

1. Finite State Machines Link.