Pinned Repositories
Auqaab-Single-Cycle-Core
Auqaab-Single-Cycle-Core is an implementation of the RV32I single-cycle RISC-V processor using Scala and Chisel. This project features a straightforward design that serves as an educational tool and a foundation for understanding the basics of RISC-V architecture and digital design using Chisel.
Basic-Operating-System
This repository contains the source code for a basic operating system (OS) project, Explore a basic OS project in C with user, file, and process management functionalities. Interact via command line. Contribute to development!
CarsNow
This repository houses the implementation of a Car Rental Management System, developed as a database project for the 4th semester of my computer science program. It includes functionalities for managing car inventory, customer data, reservations, rental transactions, and administrative tasks.
functional-programming
scala functional programming
gem5_GUI
Project Init.
hospital-management-system
hospital management system Java (DSA PROJECT)
Merl-UIT-Simulator
RISC-V simulator
RV32I-Five-Stage-Pipeline
5-stage pipelined RV32I RISC-V processor using Scala and Chisel. This project demonstrates the principles of pipelining in processor design, enhancing performance by overlapping instruction execution across multiple stages: Fetch, Decode, Execute, Memory, and Write-back. Ideal for educational purpos
Scala-Chisel-Learning-Journey
This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
SSaadAKHTAR
SSaadAKHTAR's Repositories
SSaadAKHTAR/Auqaab-Single-Cycle-Core
Auqaab-Single-Cycle-Core is an implementation of the RV32I single-cycle RISC-V processor using Scala and Chisel. This project features a straightforward design that serves as an educational tool and a foundation for understanding the basics of RISC-V architecture and digital design using Chisel.
SSaadAKHTAR/functional-programming
scala functional programming
SSaadAKHTAR/RV32I-Five-Stage-Pipeline
5-stage pipelined RV32I RISC-V processor using Scala and Chisel. This project demonstrates the principles of pipelining in processor design, enhancing performance by overlapping instruction execution across multiple stages: Fetch, Decode, Execute, Memory, and Write-back. Ideal for educational purpos
SSaadAKHTAR/Scala-Chisel-Learning-Journey
This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
SSaadAKHTAR/SSaadAKHTAR
SSaadAKHTAR/Basic-Operating-System
This repository contains the source code for a basic operating system (OS) project, Explore a basic OS project in C with user, file, and process management functionalities. Interact via command line. Contribute to development!
SSaadAKHTAR/CarsNow
This repository houses the implementation of a Car Rental Management System, developed as a database project for the 4th semester of my computer science program. It includes functionalities for managing car inventory, customer data, reservations, rental transactions, and administrative tasks.
SSaadAKHTAR/gem5_GUI
Project Init.
SSaadAKHTAR/hospital-management-system
hospital management system Java (DSA PROJECT)
SSaadAKHTAR/Merl-UIT-Simulator
RISC-V simulator
SSaadAKHTAR/oxygen