About Me: Interested in the domains of VLSI Systems and Computer Architecture. Inspired by cutting-edge research in domain-specific architectures, hardware accelerators, in-memory computing, and other areas focused on designing low-power and high-performance systems.
I am currently working as an SoC Design Verification Engineer specializing in the Design Verification of clock controllers and clock monitoring IPs for Snapdragon SoCs. I have experience curating test plans and driving verification activities to closure for multiple IPs intended for a wide range of applications across mobile, compute, and automotive applications.
I graduated from the Department of Electronics & Communication Engineering, National Institute of Technology, Karnataka, India.
I have previously interned at Qualcomm as well as at the Department of Electronics Systems Engineering (DESE), Indian Institute of Science, Bengaluru, and obtained holistic research and industry experience.
I have been an active contributor to IEEE activities both as a student as well as a professional. I currently volunteer as a member of IEEE Region10 Strategic Planning and New Initiatives Committee and as Secretary of IEEE Young Professionals Affinity Group. Previously, I have led a 400+ member strong NITK IEEE Student Branch as Chairman to organize technical and professional activities for the benefit of the student fraternity.