Pinned Repositories
Design_and_Implementation_of_High_Speed_1Kb_SRAM_Memory_Array
The project is designed using 90nm technology in Cadence Virtuoso
FIFO_MEMORY
G13_VLSI
JTAG
Technical_Seminar
Toward 5G Edge Computing for Enabling Autonomous Aerial Vehicles
Verification_Environment_for_FIFO
VLSI-Project-AXI-to-APB-Bridge
G13_VLSI
FIFO_MEMORY
Sandeshg25's Repositories
Sandeshg25/Verification_Environment_for_FIFO
Sandeshg25/Design_and_Implementation_of_High_Speed_1Kb_SRAM_Memory_Array
The project is designed using 90nm technology in Cadence Virtuoso
Sandeshg25/Technical_Seminar
Toward 5G Edge Computing for Enabling Autonomous Aerial Vehicles
Sandeshg25/G13_VLSI
Sandeshg25/JTAG
Sandeshg25/FIFO_MEMORY
Sandeshg25/VLSI-Project-AXI-to-APB-Bridge