Sarthakchandra
Sophomore@ IIIT Delhi. Avid coder with keen interests in electronic hardware, economics, & financial market analysis. Pursuing an Undergrad Degree in ECE
Indraprastha Institute Of Information Technology (South, Delhi)Delhi, India
Pinned Repositories
elysium.iiitd.edu.in
Website for IEEE IIIT Delhi's TechWeek: Elysium
v1.ieee.iiitd.edu.in
v1. Official website for IIIT Delhi's IEEE Student Branch
Adder-Pipelining
In this part, we will make two different designs of an 8-bit adder—one without pipelining and the other with pipelining and observe the effect on the maximum operating frequency and latency of the design. For Further Step by Step Instructions Check Lab5.pdf
AXI4-Lite-IP-Creation
Create a custom AXI4 Lite IP to perform the following operation Q= X/T + sqrt(α ln(N)/T)
CacheSimulator
A cache of size S with CL as the number of cache lines and block size B is to be built. S, CL, and B are in powers of 2. Write a program that allows loading into cache and searching cache using: Direct mapping Associative memory n-way set associative memory where n is a power of 2. Any programming language (of your choice) can be used.
capture-the-flage
🚩 [DES130 Minor Project] Basic single/multi-player maze game built using Processing and Arduino-controlled inputs
ComplexFloatingPoint
Code For Floating point Calculation of Complex Functions taking into account to avoid multi-driver Input
FIFO-64bit
In this part, we will learn how to implement a FIFO Memory using FIFO Generator IP with given size and customize it. We will also look into various signals and their use associated with FIFO. For more details refer to Lab6.pdf
QRFactorisation
QR Factorisition using GramSchmidt process and numpy
ZynqIP_Config
In this part, we will learn how to use IP Integrator to create a processing system-based design consisting of ARM cortex A9 cores. An abstract view of the Zynq architecture is given below. We will need the DDR3 controller for external DDR3 memory. As we are accessing the Zybo board remotely, we will be using the JTAG terminal instead of UART for the STDIN and STDO. Refer to Lab9.pdf for Step-by-Step Guide
Sarthakchandra's Repositories
Sarthakchandra/FIFO-64bit
In this part, we will learn how to implement a FIFO Memory using FIFO Generator IP with given size and customize it. We will also look into various signals and their use associated with FIFO. For more details refer to Lab6.pdf
Sarthakchandra/ZynqIP_Config
In this part, we will learn how to use IP Integrator to create a processing system-based design consisting of ARM cortex A9 cores. An abstract view of the Zynq architecture is given below. We will need the DDR3 controller for external DDR3 memory. As we are accessing the Zybo board remotely, we will be using the JTAG terminal instead of UART for the STDIN and STDO. Refer to Lab9.pdf for Step-by-Step Guide
Sarthakchandra/Adder-Pipelining
In this part, we will make two different designs of an 8-bit adder—one without pipelining and the other with pipelining and observe the effect on the maximum operating frequency and latency of the design. For Further Step by Step Instructions Check Lab5.pdf
Sarthakchandra/AXI4-Lite-IP-Creation
Create a custom AXI4 Lite IP to perform the following operation Q= X/T + sqrt(α ln(N)/T)
Sarthakchandra/CacheSimulator
A cache of size S with CL as the number of cache lines and block size B is to be built. S, CL, and B are in powers of 2. Write a program that allows loading into cache and searching cache using: Direct mapping Associative memory n-way set associative memory where n is a power of 2. Any programming language (of your choice) can be used.
Sarthakchandra/capture-the-flage
🚩 [DES130 Minor Project] Basic single/multi-player maze game built using Processing and Arduino-controlled inputs
Sarthakchandra/ComplexFloatingPoint
Code For Floating point Calculation of Complex Functions taking into account to avoid multi-driver Input
Sarthakchandra/QRFactorisation
QR Factorisition using GramSchmidt process and numpy
Sarthakchandra/DEMOLISH-A-DIY-Brick-Breaker-Game
A new and innovative Version of the Classic Game Brick Breaker complete with Arduino Based remote-controlled Pongs operating through basic electronic components, arranged in a fully programmed module with graphics reminiscent of your childhood days.
Sarthakchandra/detectron2
Detectron2 for Document Layout Analysis
Sarthakchandra/DIP
Submissions Made for DIP Assignments 2021
Sarthakchandra/DSP
Submissions made for the DSP Course
Sarthakchandra/elysium.iiitd.edu.in
Website for IEEE IIIT Delhi's TechWeek: Elysium
Sarthakchandra/FloatingPointIP
In this Lab, we will implement and verify the following function using the floating-point IP ❖ Q = (X/T) + sqrt (ln(N)/T)
Sarthakchandra/ieee.iiitd.edu.in
Official website for IIIT Delhi's IEEE Student Branch
Sarthakchandra/layout-parser
A unified toolkit for Deep Learning Based Document Image Analysis
Sarthakchandra/Matrix-Multiplication
Sarthakchandra/MealyFSM
In this Lab, we will look into how to implement Mealy FSM using Verilog. As an example, we will be designing a 11011 sequence detector with an overlap.
Sarthakchandra/MooreFSM
In this Lab, we will design a non-overlapping sequence detector (11011) using Moore type FSM. For Further Step-by-Step procedure refer to Lab5.pdf
Sarthakchandra/Rom-using-BRAM
In this part, we will learn about how to implement a ROM using the Block Memory Generator IP and look at how we can customize the IP according to our needs.
Sarthakchandra/ROSNet-A-WMN-based-Framework-using-UAVs-and-Ground-Nodes-for-Disaster-Management
Aim is to develop a Multi Hop Communication using UAVs. The system would act as a delay tolerant network gathering messages from one location and delivering them to another. The Network is Ad-Hoc without the need for continuous communication between the UAVs.
Sarthakchandra/saddahack.tech