Pinned Repositories
chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
chisel-template
A template project for beginning new Chisel work
chisel3
Chisel 3
connectal
Connectal is a framework for software-driven hardware development.
cs231n.github.io
Public facing notes page
Deep-Learning-Processor-List
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
ece4750-tut3-pymtl
ECE 4750 Tutorial 3: PyMTL Hardware Modeling Framework
fpu
synthesiseable ieee 754 floating point library in verilog
haddoc2
Caffe to VHDL - Institut Pascal
Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
SasinduGeemal's Repositories
SasinduGeemal/chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
SasinduGeemal/chisel-template
A template project for beginning new Chisel work
SasinduGeemal/chisel3
Chisel 3
SasinduGeemal/connectal
Connectal is a framework for software-driven hardware development.
SasinduGeemal/cs231n.github.io
Public facing notes page
SasinduGeemal/Deep-Learning-Processor-List
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
SasinduGeemal/ece4750-tut3-pymtl
ECE 4750 Tutorial 3: PyMTL Hardware Modeling Framework
SasinduGeemal/fpu
synthesiseable ieee 754 floating point library in verilog
SasinduGeemal/haddoc2
Caffe to VHDL - Institut Pascal
SasinduGeemal/Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
SasinduGeemal/nasti-ddrx-mc
NASTI slave compliant DDRx memory controller.
SasinduGeemal/NetFPGA-1G-CML
Information about the NetFPGA 1G-CML card
SasinduGeemal/NeuralHDL
SasinduGeemal/OP2-Common
OP2: open-source framework for the execution of unstructured grid applications on clusters of GPUs or multi-core CPUs
SasinduGeemal/OpenED
Open source semiconductor framework for design and develop your own custom micro-chips
SasinduGeemal/OPS
OPS is an API with associated libraries and preprocessors to generate parallel executables for applications on mulit-block structured meshes.
SasinduGeemal/processors
Natural Language Processors
SasinduGeemal/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
SasinduGeemal/riscv_fpga
An implementation of the basic RISC V architecture, specialized for Xilinx FPGAs in its first iteration.
SasinduGeemal/SDN
Uses POX to interact with the SDN controller
SasinduGeemal/verilog-ethernet
Verilog Ethernet components
SasinduGeemal/verilog_fixed_point_math_library
Fixed Point Math Library for Verilog
SasinduGeemal/Vivado-KMeans
Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
SasinduGeemal/zynqnet
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"