twitchcore
A RISC-V core, first in Python, then in Verilog, then on FPGA.
TODO
- Fix unaligned loads/stores
- Make pipelining work
- Add M instructions for fast multiply and divide
- Add better introspection
TODO (later)
- Many ROBs like M1 go very fast
A RISC-V core, first in Python, then in Verilog, then on FPGA.