/OFDM_Verilog

This repo is about implementing OFDM transmitter on FPGA (Zedboard) using Verilog language and Vivado simulator

Primary LanguageVerilog

OFDM_Verilog

This repo is about implementing OFDM transmitter on FPGA (Zedboard) using Verilog language and Vivado simulator The project has 3 milstones Firstly is the OFDM Tx alone it has a bandwidth of 36 KHz starting from zero frequency Secondly is the Up converter and the Up sampler which has a center frequency at 84 KHz Finally the integration between two blocks. The center frequency is 84 KHz with 72KHz bandwidth