Pinned Repositories
2D-convolution-Simulation
2D convolution module to perform convolution operation between a matrix and kernel
32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
AXI
VIP for AXI Protocol
basic_verilog
Must-have verilog systemverilog modules
Codes_By_Me
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Design-verification
UVM and Systemverilog based test benches for functional verification of a RAM module
easyUVM
A simple UVM example with DPI
iic_uvm_tb
I2C testbench using the UVM
my-systemverilog-examples
A place to keep my synthesizable SystemVerilog code snippets and examples.
Shakthi079's Repositories
Shakthi079/basic_verilog
Must-have verilog systemverilog modules
Shakthi079/iic_uvm_tb
I2C testbench using the UVM
Shakthi079/my-systemverilog-examples
A place to keep my synthesizable SystemVerilog code snippets and examples.
Shakthi079/2D-convolution-Simulation
2D convolution module to perform convolution operation between a matrix and kernel
Shakthi079/32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
Shakthi079/AXI
VIP for AXI Protocol
Shakthi079/Codes_By_Me
Shakthi079/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Shakthi079/Design-verification
UVM and Systemverilog based test benches for functional verification of a RAM module
Shakthi079/easyUVM
A simple UVM example with DPI
Shakthi079/formal_hw_verification
Trying to verify Verilog/VHDL designs with formal methods and tools
Shakthi079/fourier-transmitter
A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.
Shakthi079/FPGA-ftdi245fifo
FPGA-based USB fast communication using FT232H/FT600 chip.
Shakthi079/INT_FP_MAC
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
Shakthi079/libgcrypt
GNU Crypto library
Shakthi079/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
Shakthi079/SoC-Design-DDR3-Controller
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
Shakthi079/SystemVerilog-Implementation-of-DDR3-Controller
The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.
Shakthi079/uvm-basics
my UVM training projects
Shakthi079/uvm_course_cadence
Labs for UVM in Cadence Xcelium
Shakthi079/UVM_TestBench_For_Ring_Counter
Complete UVM TestBench For Verification Of Ring (Onehot) Counter
Shakthi079/verilog-axis
Verilog AXI stream components for FPGA implementation
Shakthi079/verilog-dsp
Verilog digital signal processing components