- This is a (7, 4) Cyclic Encoder using a Linear Feedback Shift Register in VHDL. Output is produced on the 5th clock cycle, after 4 shifts.
- Code copied from my answer on the Electrical Engineering Stack Exchange.
- design.vhd contains the VHDL design file and testbench.vhd contains a simple VHDL testbench.
- Here is a live demonstration of the project on EDA Playground.
- To do: Cyclic Decoder in VHDL. Make the design parameterisable. Make the testbench self-checking.