ShashankVM's Stars
chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
tukl-msd/DRAMSys
DRAMSys a SystemC TLM-2.0 based DRAM simulator.
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
pulp-platform/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
black-parrot/black-parrot
A Linux-capable RISC-V multicore for and by the world
isocpp/CppCoreGuidelines
The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++
intel/systemc-compiler
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
gnuradio/gnuradio
GNU Radio – the Free and Open Software Radio Ecosystem
cpc/openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
zachjs/sv2v
SystemVerilog to Verilog conversion
YosysHQ/yosys
Yosys Open SYnthesis Suite
YosysHQ/sby
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
whatmough/CHIPKIT
CHIPKIT: An agile, reusable open-source framework for rapid test chip development
timvideos/flterm
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
dhylands/rshell
Remote Shell for MicroPython
gpgpu-sim/gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
chipsalliance/dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
agra-uni-bremen/riscv-vp
RISC-V Virtual Prototype
NVlabs/matchlib
SystemC/C++ library of commonly-used hardware functions and components for HLS.