ShashankVM's Stars
diffblue/hw-cbmc
The HW-CBMC and EBMC Model Checkers for Verilog
hernanponcedeleon/Dat3M
A verification tool for many memory models
wyvernSemi/vproc
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
ShashankVM/formal_verif_ecc
Formal Verification of RVECC Error Correcting Code Hardware
chipsalliance/VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
cloudxcc/PDVL_Examples
Example designs using the Programming Design and Verification Language (PDVL)
NVlabs/litmustestgen
Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)
johnwickerson/memalloy
Memory consistency modelling using Alloy
janestreet/learn-ocaml-workshop
Exercises and projects for Jane Street's OCaml Workshop
askvortsov1/hardcaml-mips
daniellustig/coatcheck
COATCheck
ctrippel/TriCheck
janestreet/hardcaml
Hardcaml is an OCaml library for designing hardware.
bespoke-silicon-group/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
janestreet/hardcaml_verify
Hardcaml Verification Tools
bsc-loca/sargantana
Risto97/VeriSC
SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
jakkra/ZSWatch
ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.
LX-IC/VP
toddmaustin/bringup-bench
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
TerosTechnology/vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
PrincetonUniversity/AutoSVA
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
sampsyo/cs6120
advanced compilers
YosysHQ-GmbH/SVA-AXI4-FVIP
YosysHQ SVA AXI Properties
PacktPublishing/Learn-FPGA-Programming
Learn FPGA Programming, published by Packt
selvakumarjawahar/reactorlib
platformio/platformio-core
Your Gateway to Embedded Software Development Excellence :alien:
UCLA-VAST/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
google/CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
kactus2/kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.