SystemC-UVM verification framework and CMake based HW build system
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VeriSC provides an easy way to verify your hardware with SystemC, with an option to use SystemC-UVM and additional libraries to enhance your verification environment. It is possible to simulate your RTL code with Verilator or Synopsys VCS simulators.
The project is composed of multiple parts:
- CMake build system for RTL and/or SystemC simulation, provides a structure ways for organizing your RTL projects and testbenches with CMake recipes, making IP blocks easy to package and distribute.
- It allows proper SystemC verification of RTL code, similar to what SystemVerilog can provide. It supports UVM enviroments, Constraint Randomization, Coverage, RTL simulation using external libraries and tools. All that at no cost using only open source and free tools and libraries, with an optional support for commercial RTL simulators.
- Several Universal Verification Components (UVCs) are provided for standard interconnect protocols (APB, I2C, Picorv32 NMI... tbc)
VeriSC will build all of the needed dependencies automatically, there are only 2 dependencies that will not be built:
- Relatively recent version of C compiler that can compile GCC 12.2
- CMake version 25.1 or greater
- Autotools
CMake can also be installed by running the script scripts/install_cmake.sh After which CMake will be installed and source.sh will be generated to add CMake to path. TODO change
In order to install VeriSC you need to follow these steps:
- Clone the repo
git clone https://github.com/Risto97/VeriSC.git
- Make a build directory
cd VeriSC mkdir build - Invoke CMake to configure the build, provide CMAKE_INSTALL_PREFIX=<path> pointing to the path you want VeriSC installed, optional variables are VCS_HOME=<path-to-vcs> that points to your VCS installation directory and CMAKE_CXX_STANDARD=[11,14,17,20] specifying the C++ standard in which to compile the libraries
cmake -DCMAKE_INSTALL_PREFIX=/tools/verisc -DVCS_HOME=/path/to/vcs ../
- After CMake has finished without errors, you can build and install the project, running with -j [number of jobs] will speed up the installation
make -j16 install
- It is required to set the enviroment variable to point to the installation directory of VeriSC, TODO change VERISC_HOME -> VERISC_HOME
export VERISC_HOME=/tools/verisc
Now the VeriSC is installed with all of the libraries and tools
There are few examples that are provided in the repository. They are placed in examples directory.
All the examples can be run by following these steps
- CD into the example directory and create a build directory
cd examples/nmi2apb mkdir build cd build
- Configure the project with CMake
cmake ../
- Run the simulation with Verilator or VCS, with make run use -j [number of jobs] to accellerate building
make -j16 run # Verilator make vrun # VCS
Example to show how to verify a simple RTL module with SystemC-UVM environment using constrained randomization and functional coverage. The RTL can be simulated with Verilator or VCS
It is a simplest example on how to simulate RTL together with SystemC testbench, but without UVM and other libraries
- Move Verilating in build phase from configure phase
- Finalize CRAVE support
- Allow different constraint solvers, currently Z3 and CUDD
- Add Additional Examples
- No verilog example
- Multiple verilog top level connected with SystemC
- CRAVE example
- VeriSC installation as CMake Package
- Support Verilator version 5 and greater
- Support C++ 20
- Integrate SC enhance for better forks in SystemC
- Clang support
- Xcelium support
See the open issues for a full list of proposed features (and known issues).
Copyright CERN, ALL RIGHTS RESERVED.
See LICENSE for more information.
Temporary license until I decide on more permissive one
Your Name - risto.pejasinovic@gmail.com - risto.pejasinovic@cern.ch