Pinned Repositories
Digital-Soc-Design
This Repository contains the complete Soc Design of Picorv32a
DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)
RISC-V-Physical-Design-Implementation
The RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s a three-stage pipelined processor which executes 32-bit instructions in program order.
VSD_TCL_workshop
ShyamRazesh's Repositories
ShyamRazesh/DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)
ShyamRazesh/Digital-Soc-Design
This Repository contains the complete Soc Design of Picorv32a
ShyamRazesh/RISC-V-Physical-Design-Implementation
The RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s a three-stage pipelined processor which executes 32-bit instructions in program order.
ShyamRazesh/VSD_TCL_workshop