Issues
- 0
SiTCP 10G implementation
#224 opened - 1
PyPI Maintanence
#222 opened - 2
Firmware compilation error with always_latch
#219 opened - 1
- 0
- 0
- 3
- 1
Mismatched function name for X-ray machine
#185 opened - 10
Q: Initialization procedure
#175 opened - 0
Unnecessary NTC Register temperature logging
#170 opened - 4
- 2
- 3
Add markers for sbus examples
#152 opened - 1
SiTCP performance regression
#123 opened - 8
- 1
Redefine TDC words data format
#116 opened - 1
Use Black for formating
#113 opened - 1
DeprecationWarning for ABC
#110 opened - 6
- 2
default_nettype
#108 opened - 5
- 4
Error when using Serial with python3
#101 opened - 2
Add simple example for bdaq53 board
#93 opened - 0
Confusing exception error message
#92 opened - 2
Clock domain crossing issues in m26_rx
#91 opened - 0
Q: Tune tlu
#89 opened - 0
Annoying warning from basil.TL.Serial
#86 opened - 7
TCP timeout
#85 opened - 3
- 1
Module level logging
#78 opened - 1
Driver for si5324
#77 opened - 7
StdRegister offset
#76 opened - 6
- 0
bug in log print
#73 opened - 8
- 0
basil.TL.TransferLayer.Serial.query() doesn't handle receive buffer with old data properly
#62 opened - 10
Test of SCPI fails
#61 opened - 1
TDC: wrong TDC_OUT
#59 opened - 1
- 0
- 3
CONF_DONE not working in seq_gen_core.v
#54 opened - 9
Configuration yaml not working
#53 opened - 0
- 2
Change firmware folder structure
#51 opened - 1
SiTCP.py bug
#50 opened - 5
Setting power gives error
#48 opened - 11
Autoupload to PyPI
#47 opened - 1
Test for TDC
#42 opened - 1
TL.SiUart needs changes
#39 opened - 4
Basil on PyPI
#38 opened