高级硬件设计(HLS)卷积神经网络加速器
1.实现对多通道(16通道)卷积和池化计算进行加速;
2.实现卷积与池化的深度融合。
- 使用HLS工具,对其进行优化(如使用pipeline、partition等)。
1.主要的实现在fpga_lab_2_cnn/conv.cpp
中.测试代码为fpga_lab2_cnn/conv_test.cpp
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A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.
C++