Pinned Repositories
32-bit-RISC-V-Cpu-Core
8-bit-ALU-in-verilog
8-bit ALU in Verilog.
anycore-riscv-src
The RTL source for AnyCore RISC-V
CMOS-NOR-Gate_IITH-Hackathon
CMOS Implemented NOR Gate is designed using Synopsys custom design tools.
Complete-Python-3-Bootcamp
Course Files for Complete Python 3 Bootcamp Course on Udemy
embedded-systems-study-group_fork
Notes and Assignments of embedded systems study group
eSim
This repository contain source code for new flow of FreeEDA now know as eSim
Integrating-Peripheral-with-Core
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Sidshx's Repositories
Sidshx/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Sidshx/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Sidshx/8-bit-ALU-in-verilog
8-bit ALU in Verilog.
Sidshx/anycore-riscv-src
The RTL source for AnyCore RISC-V
Sidshx/CMOS-NOR-Gate_IITH-Hackathon
CMOS Implemented NOR Gate is designed using Synopsys custom design tools.
Sidshx/Complete-Python-3-Bootcamp
Course Files for Complete Python 3 Bootcamp Course on Udemy
Sidshx/embedded-systems-study-group_fork
Notes and Assignments of embedded systems study group
Sidshx/eSim
This repository contain source code for new flow of FreeEDA now know as eSim
Sidshx/Integrating-Peripheral-with-Core
Sidshx/platformio-projects
Arduino-powered projects built using PlatformIO IDE extension in Visual Studio Code
Sidshx/sra-board-hardware-design
ESP32-based Development Board for Robotics and Embedded Applications
Sidshx/Ultrasonic_radar
Sidshx/walle_testing
Testing Walle