Pinned Repositories
2022HWC
A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
CPU_Design_MIPS
《CPU设计实战》学习记录及代码
GM_PHD_Filter
GM-PHD filter in target tracking
hls4ml
Machine learning on FPGAs using HLS
MAERI_bsv
MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
MAERI_bsv_isca2018
MAERI public release
maestro
An analytical cost model evaluating DNN mappings (dataflows and tiling).
NPU-on-Vivado-HLS
A NPU designed by Vivado HLS
SiamR-CNN
Siam R-CNN two-stage re-detector for visual object tracking
SinnLiu's Repositories
SinnLiu/CPU_Design_MIPS
《CPU设计实战》学习记录及代码
SinnLiu/2022HWC
SinnLiu/A-convolution-kernel-implemented-by-Vivado-HLS
This project implements a convolution kernel based on vivado HLS on zcu104
SinnLiu/hls4ml
Machine learning on FPGAs using HLS
SinnLiu/MAERI_bsv
MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
SinnLiu/MAERI_bsv_isca2018
MAERI public release
SinnLiu/maestro
An analytical cost model evaluating DNN mappings (dataflows and tiling).
SinnLiu/NPU-on-Vivado-HLS
A NPU designed by Vivado HLS
SinnLiu/SiamR-CNN
Siam R-CNN two-stage re-detector for visual object tracking
SinnLiu/SkyNet
iSmart3 https://github.com/TomG008/SkyNet
SinnLiu/ThunderGP
HLS-based Graph Processing Framework on FPGAs
SinnLiu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
SinnLiu/tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
SinnLiu/AI-Chip
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
SinnLiu/AiLearning
AiLearning: 机器学习 - MachineLearning - ML、深度学习 - DeepLearning - DL、自然语言处理 NLP
SinnLiu/CPU-on-Vivado-HLS
A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
SinnLiu/datamining
SinnLiu/Free-TPU
Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.
SinnLiu/gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
SinnLiu/ics-pa
SinnLiu/Machine_Learning_Resources
:fish::fish::fish: 机器学习面试复习资源
SinnLiu/QtMips
MIPS CPU emulator
SinnLiu/qtrvsim
RISC-V CPU simulator for education purposes
SinnLiu/resnet_fpga
UCSD CSE 237D Spring '20 Course Project
SinnLiu/rethinking-network-pruning
Rethinking the Value of Network Pruning (Pytorch) (ICLR 2019)
SinnLiu/SinnLiu
Config files for my GitHub profile.
SinnLiu/sinnliu.github.io
SinnLiu/spooNN
FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
SinnLiu/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
SinnLiu/YOLOv3-model-pruning
在 oxford hand 数据集上对 YOLOv3 做模型剪枝（network slimming）