Pinned Repositories
SoC-Tapeout-Tutorial
A repository hosting the source of SoC-tapeout babysitting tutorial.
3d_diffusion_soc
C_compile_template
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
edge-training-SoC
Online edge training SoC Tapeout recording
Modern_SoC_Design_Note
RISC-V-GCC-TOOLCHAIN
RISC-V gcc toolchain compatible with CORE-V family, fork from CVA6 repo
Siris-Li.github.io
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
FP8-Emulation-Toolkit
PyTorch extension for emulating FP8 data formats on standard FP32 Xeon/GPU hardware.
Siris-Li's Repositories
Siris-Li/Modern_SoC_Design_Note
Siris-Li/C_compile_template
Siris-Li/RISC-V-GCC-TOOLCHAIN
RISC-V gcc toolchain compatible with CORE-V family, fork from CVA6 repo
Siris-Li/SoC-Tapeout-Tutorial
A repository hosting the source of SoC-tapeout babysitting tutorial.
Siris-Li/edge-training-SoC
Online edge training SoC Tapeout recording
Siris-Li/3d_diffusion_soc
Siris-Li/Siris-Li.github.io
Siris-Li/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux