Pinned Repositories
analysis-model
A library to read static analysis reports into a Java object model
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chisel-release
Chisel release tooling
chisel-tutorial
chisel tutorial exercises and answers
esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
linux-on-litex-vexriscv
Linux on LiteX-VexRiscv
NaxRiscv
SpinalHDL
Scala based HDL
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
SoCScholar's Repositories
SoCScholar/analysis-model
A library to read static analysis reports into a Java object model
SoCScholar/cloudcomputing
Vorlesung Cloud Computing
SoCScholar/cocotb-BSHL
Enables access from cocotb/Pyuvm to SystemVerilog Verification IP. Besides re-usable code, this repo contains a simple example implementation
SoCScholar/cocotbext-pcie
PCI express simulation framework for Cocotb
SoCScholar/code-coverage-api-plugin
Deprecated Jenkins Code Coverage Plugin
SoCScholar/constellation
A Chisel RTL generator for network-on-chip interconnects
SoCScholar/Constellation_NoC
SoCScholar/core
:house_with_garden: Open source home automation that puts local control and privacy first.
SoCScholar/cutlass
CUDA Templates for Linear Algebra Subroutines
SoCScholar/cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
SoCScholar/hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
SoCScholar/heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
SoCScholar/hm-aemy.github.io
SoCScholar/HotSniper
An EDA toolchain for interval thermal simulations of 2D multi-/many-cores in an open system.
SoCScholar/IIC-OSIC-TOOLS
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
SoCScholar/NoxyGen
Generates NoC in verilog using configuration Graph
SoCScholar/openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
SoCScholar/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
SoCScholar/opentitan
OpenTitan: Open source silicon root of trust
SoCScholar/processor-trends
SoCScholar/riscv-isa-sim
Spike, a RISC-V ISA Simulator
SoCScholar/riscv-vector
Vector Acceleration IP core for RISC-V*
SoCScholar/RSD_OoO_CPU
RSD: RISC-V Out-of-Order Superscalar Processor
SoCScholar/seal5
Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization
SoCScholar/tacos
TACOS: [T]opology-[A]ware [Co]llective Algorithm [S]ynthesizer for Distributed Machine Learning
SoCScholar/tapasco
The Task Parallel System Composer (TaPaSCo)
SoCScholar/Thesis_documentation
A minimal & modern LaTeX template for your (bachelor's | master's | doctoral) thesis
SoCScholar/uciedigital
Pure digital components of a UCIe controller
SoCScholar/verilator
Verilator open-source SystemVerilog simulator and lint system
SoCScholar/x-heep_EPFL
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V