SreekashUS/aqua-soc

SoC based on RISCV ISA

Aqua SoC

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System on Chip(SoC) based on RISCV ISA with various requirements and µ-arch

Getting started

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• Starting with base RV32I instruction set which supports minimal program execution.

Architectures

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• Starting with RV32I (codename: aqua_pygmy)
  • Supports pipelined execution
  • Has minimal execution unit ( aluRv32i )
  • Register file of type 2R1W

TODO

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AquaPygmy

• General:
  • Write Hazard logic
    • Data Hazards
    • Control Hazards
• For ASIC:
  • Synthesize proper SRAM macro for register file
• For FPGA:
  • Use Embedded memory or BRAM for register file with multiport access