Why VALID mode is removed from PE registers?
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During configuration when the chip is clock-gated, using VALID mode will prevent the register taking values. This mode was proven to be very critical when I was testing the Jade chip.
So the question is: is VALID got renamed to DELAY mode, or we can't never clock gate the register in the future? If that's the case, there should be extra graph analysis to make sure that register used in counter should never be used inside PE since you can't clock gate it.
I removed this because the plan was to add this as a garnet pass.
My impression was that the enable signal should not come from the routing fabric. @Kuree is this not the case? We discussed this ~1 month ago.
The way we should do this is by adding a pass to insert the clock gating into all the registers in the PE and then wiring them to the stall signal.
@leonardt do the magma registers generated from peak have clock enables?
The clock enable signal should come from the control logic which is separate from the routing fabric. My concern is that we are going to lose the ability to stall the registers at control level.
@Kuree, what are you requesting? Are you asking whether garnet can do this pass correctly?
I'm asking what's the plan for clock gating registers in PE.
Do you want control over which registers get clock gated? If not, then the plan (like Raj said) is to have a garnet pass which hooks up a stall signal to all of the registers which (should be) controlled by the global controller. @rsetaluri, can you confirm?
I was not aware of the plan. If that's the case it should work well.
Closing