This is a naive implementation of an "Alternating Step Generator" (ASG) to produce bit sequences with a very long period. ASGs are characterized by their easy implementability in hardware, which is why they are a nice example for the use of SpinalHDL. The project uses the Rings library [1] to check whether a given polynomial is primitive. For this purpose, complicated algorithms such as the quadratic sieve (to factorize numbers) and arithmetic for finite fields are used. Once the calculation is complete, an efficient hardware description (Verilog and VHDL) is generated.
An ASG consists of three different "Linear Shift Feedback Registers" (LSFR), which must be coupled appropriately. Each LSRF is based on a specific polynomial that must have certain algebraic properties. In order to have the full period length, it must be "primitive". Let p be a polynomial with coefficients on Z/2Z, i.e. the coefficients are either 0 or 1 and modulo. If p is irreducible, i.e. there are no polynomials r and s with at least degree 1, such that p = r * s, then (Z/2Z)[x]/(q) is a (finite) field. This means that you can calculate with the remainders mod q of the polynomials (Z/2Z)[x] as with "normal" real numbers (add, subtract, multiply and divide). If all elements of this field can be written as powers of the unknown x, i.e. 1,x,x^2,x^3, ..., then q is called "primitive".
These algebraic properties must first be checked in order to obtain a usable (full period) LSFR for the ASG. This is done in software at the time the hardware is generated, i.e. a polynomial is configured and the software checks the properties "irreducible" and "primitive". If everything is OK, the corresponding hardware, i.e. an LSFR or ASG, is generated. This shows the advantages of a meta-HDL such as SpinalHDL, which uses the strengths of the software world (extensive libraries, high flexibility) to generate extremely configurable hardware descriptions.
See TinyTapeOut 06 (https://github.com/TinyTapeout/tinytapeout-06/tree/main/projects/tt_um_SteffenReith_ASGTop) for an ASIC-implementation.
[1] Stanislav Poslavsky, Rings: An efficient Java/Scala library for polynomial rings, Computer Physics Communications, Volume 235, 2019, Pages 400-413, doi:10.1016/j.cpc.2018.09.005