Surepuls

Surepuls's Stars

• tcltk/tcl

  The Tcl Core. (Mirror of core.tcl-lang.org)

  Language:C674187

• greenblat/vhdl2v

  vhdl translator to verilog

  Language:Python1

• xobs/alliance

  Mirror / work on lip6 Alliance

  Language:C2

• ArcaneNibble/yavhdl

  Yet Another VHDL tool

  Language:Yacc313

• FelixVi/PurpleMesa

  A VHDL parser based on flex and bison

  Language:C++81

• antlr/antlr4

  ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

  Language:Java17k3.3k

• Nic30/hdlConvertor

  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

  Language:C++28166

• dalance/sv-parser

  SystemVerilog parser library fully compliant with IEEE 1800-2017

  Language:Rust39753

• chipsalliance/Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++35768

• chipsalliance/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++336

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.3k203

• accellera/uvm

  Language:SystemVerilog3825

• pyuvm/pyuvm

  The UVM written in Python

  Language:Python36570

• Paebbels/pyVHDLParser

  Streaming based VHDL parser.

  Language:Python7815

• VHDL/Interfaces

  Interface definitions for VHDL-2019.

  122

• VHDL/CoreLib

  A VHDL Core Library.

  172

• VHDL/pyVHDLModel

  An abstract language model of VHDL written in Python.

  Language:Python489

• MikePopoloski/pyslang

  Python bindings for slang, a library for compiling SystemVerilog

  Language:Python457

• nickg/nvc

  VHDL compiler and simulator

  Language:VHDL63277

• slaclab/surf

  A huge VHDL library for FPGA development

  Language:VHDL32355

• VLSI-EDA/PoC

  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  Language:VHDL54193

• kevinpt/vhdl-extras

  Flexible VHDL library

  Language:VHDL17941

• BNFC/bnfc

  BNF Converter

  Language:TeX584165

• gtkwave/gtkwave

  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

  Language:C626116

• UVVM/UVVM

  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

  Language:VHDL36190

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL722261

• VHDL-LS/rust_hdl_vscode

  VHDL Language Support for VSCode

  Language:TypeScript5017

• VHDL-LS/rust_hdl

  Language:Rust33665

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.4k872

• svunit/svunit

  Language:SystemVerilog18261