Pinned Repositories
axi_components
A mixture of AXI components and tests
cv32e40p_tuni_fpga
FPGA based CV32E40P platform for use on TUNI projects.
fpga_uart
UART implemented for use in FPGA projects and for fun
FRiscV
RV32I Implementation
jtag_vpi
TCP/IP controlled VPI JTAG Interface.
linux_kernel_drivers
Repo to practice writing Linux kernel drivers
pikuma_computer_graphics
Computer graphics programming course from https://pikuma.com/courses/learn-3d-computer-graphics-programming
pulp_axi
Forked repo of AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
pulp_common_cells
Common SystemVerilog components
pulp_common_verification
SystemVerilog modules and classes commonly used for verification
T-Szymk's Repositories
T-Szymk/pikuma_computer_graphics
Computer graphics programming course from https://pikuma.com/courses/learn-3d-computer-graphics-programming
T-Szymk/axi_components
A mixture of AXI components and tests
T-Szymk/cv32e40p_tuni_fpga
FPGA based CV32E40P platform for use on TUNI projects.
T-Szymk/fpga_uart
UART implemented for use in FPGA projects and for fun
T-Szymk/FRiscV
RV32I Implementation
T-Szymk/jtag_vpi
TCP/IP controlled VPI JTAG Interface.
T-Szymk/linux_kernel_drivers
Repo to practice writing Linux kernel drivers
T-Szymk/pulp_axi
Forked repo of AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
T-Szymk/pulp_common_cells
Common SystemVerilog components
T-Szymk/pulp_common_verification
SystemVerilog modules and classes commonly used for verification
T-Szymk/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
T-Szymk/sync_fifo
Synchronous FIFO implemented in VHDL
T-Szymk/timing_constraints_testbed
project to practise defining timing constraints on FPGA
T-Szymk/UARTMonitor
Command line tool to monitor UART comms using USB to RS232
T-Szymk/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
T-Szymk/VGA_Controller
VGA controller written in VHDL (targeted at Digilent Arty A7-100T)
T-Szymk/Vitis-Tutorials
Vitis In-Depth Tutorials
T-Szymk/vivado_cutom_ip
testing creation of a custom AXI peripheral to be used with a Zynq