/*
Copyright (c) 2014, Intel Corporation
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*/
Contents:
--------
This repository includes:
bin/
certify_as_golden: Accepts most recent regression results as "golden".
diff_golden: Shows difference between most recent regression results and "golden" regression
results.
m4_config.m4: Used by M4-wrapped run.
make_all: Build SVGen.
make_regress_all: make_all and run regressions.
post_m4: Used by M4-wrapped run.
pre_m4: Used by M4-wrapped run.
regress_clean: Delete results of regression run.
run: Runs a regression test.
run_m4: Runs M4 wrapper on a .tlv file.
svgen: SVGen. This is a thin wrapper around the SVGen Java application that supports
the use of M4.
test_svgen: The executable for each regression test. It runs M4 if needed and SVGen.
test_vcs: Some regression tests can run in simulation and could be modified to use this
instead of test_svgen to run SVGen (+M4 if needed) and VCS simulation.
tlv_repo_context.pm: Library file for other executables.
CMakeList: Build collateral used by cmake.
Docs/: Documentation, mostly diagrams of SVGen data structures. Some docs are likely
a bit obsolete.
examples/: A directory containing regression tests (.tlv examples).
(Tests are lame, since Intel-proprietary code was stripped.)
m4/: Library files of M4 content for M4-extended .tlv files.
README.txt/: This file.
regression/: Collateral defining regression tests.
src/: SVGen source files (including some 3rd party open source code).
verilog/: Verilog include content used by generated SV.
Requirements:
------------
For build and run:
/usr/bin/cmake
/usr/bin/perl
/usr/bin/java
/usr/bin/m4 (for those .tlv files that use it)
For development:
/usr/bin/meld
Build:
-----
In {local-clone-dir}
> make_all
(which does):
- /usr/bin/cmake . (version 2.8.7)
- make
- make install
Test:
----
In {local-clone-dir}
> ctest -R <test-name>
Log written to ./Testing/Temporary/LastTest.log
Tests are defined in ./regression/CMakeLists.txt
Tests run ./bin/test_svgen <test-name> which picks up where ./bin/make_all leaves off. It runs
SVGen on the .tlv code to produce .sv. Some generated .sv can be run in simulation.
./bin/test_vcs was created to run test_svgen and then simulate. This obviously would require
a simulator, so it is not used by default. test_svgen writes output to
"regress/gen/<test-name>".
Regression:
----------
In {local-clone-dir}
> /usr/bin/ctest -j10 (10-way parallel)
(Output written to "run/gen".)
> ./bin/diff_golden
> git commit -m "message"
> git pull
> ./bin/certify_as_golden (if okay)
> git commit -m "golden certification"
> git push
Issues:
------
- Build process has dependency issues. Must remove /build to force rebuild.
- Verilog content is assumed that is not included. Specifically, there is no
definition for `GATER(...) macro (which has proprietary heritage).
- Support for state signals and $ANY is disabled since support for
TL-X 2a is not complete.
- Regressions tests are extemely weak (with the loss of proprietary tests).