RISC-V pronounced as “RISC-five”, is an open-source standard Instruction Set Architecture (ISA), designed based on Reduced Instruction Set Computer (RISC) principles. With a flexible architecture to build systems ranging from a simple microprocessor to complex multi-core systems, RISC-V caters to any market. The RISC-V ISA provides two specifications, one, the User Level Instructions which guides in developing simple embedded systems and connectivity applications and two, the Privilege Level Instructions which guides in building secure systems, kernel, and protected software stacks. RISC-V currently supports three privilege levels, viz.. Machine/Supervisor/User, with each level having dedicated Control Status Registers (CSRs) for system state observation and manipulation. In addition, RISC-V provides 31 read/write registers. While all can be used as general-purpose registers, they have dedicated functions as well. RISC-V is divided into different categories based on the maximum width of registers the architecture can support, for example, RV32 (RISC-V 32) provides registers whose maximum width is 32-bits and RV64 (RISC-V 64) provides registers whose maximum width is 64-bits. Processors with larger register widths can support instructions and data of smaller widths. So an RV64 platform supports both RV32 and RV64