Talha-Ahmed-1

GSoC'22 | Software Engineer Research Assistant | PhD Scholar @ Sungkyunkwan University

@merledu Pakistan

Pinned Repositories

Buraq-compressed-assembler
This is the compressed assembler for RISC-V.
Language:Python3 1 13
nucleusrv
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
Language:C60 3 2323
SoC-Now-Generator
An open source Mini SoC Generator which will generate SoC based on parameters.
Language:Verilog11
Aghaz-SoC
Rocket Chip Generator
Language:Scala10
Android-SMS-Sender
Language:HTML10
compressed-rv32
Language:C++00
mdu_rv32
Multiplication and Division Unit for RISCV32 Core
Language:Scala01
Shaheen-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
Language:TeX20
SoC-Now-Generator
An open source Mini SoC Generator which will generate SoC based on parameters.
Language:Verilog00
SPI-Chisel
Language:Verilog2 1 11

Talha-Ahmed-1's Repositories

Talha-Ahmed-1/SPI-Chisel
Language:Verilog2 1 11
Talha-Ahmed-1/SuperSHA3
RISCV Based SHA3-256 Accelerator
Language:Scala12
Talha-Ahmed-1/compressed-rv32
Language:C++00
Talha-Ahmed-1/mdu_rv32
Multiplication and Division Unit for RISCV32 Core
Language:Scala01
Talha-Ahmed-1/SoC-Now-Generator
An open source Mini SoC Generator which will generate SoC based on parameters.
Language:Verilog00
Talha-Ahmed-1/azadi
Azadi is an SoC with 32 bit RISC-V CPU core.
Talha-Ahmed-1/Blackbox
Language:Scala0 0
Talha-Ahmed-1/buraq_mini
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
Talha-Ahmed-1/Burq-Suite
An All in one RISC-V Suite.
Talha-Ahmed-1/caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
Talha-Ahmed-1/caravel_soc_now
Language:Verilog0 0
Talha-Ahmed-1/chiV
Verilog IP Blackbox generator for CHISEL
Language:Python1 0
Talha-Ahmed-1/comp-instr-encoder
This is the compressed instruction encoder for RISC-V.
Language:Python
Talha-Ahmed-1/CoreFPU
Language:C++
Talha-Ahmed-1/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
Talha-Ahmed-1/fpu_rv32
Floating Point Unit for RV32 in CHISEL
Language:C++1 02
Talha-Ahmed-1/jigsaw
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
Language:Scala0 0
Talha-Ahmed-1/nucleusrv
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
Language:C0 0
Talha-Ahmed-1/OpenRAM
An open-source static random access memory (SRAM) compiler.
Talha-Ahmed-1/picofoxy
Pipelined In-order Core for Artix-7 Arty-35T board
Language:Verilog1
Talha-Ahmed-1/Scala-Chisel-Learning-Journey
This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
Language:Jupyter Notebook
Talha-Ahmed-1/SoC-Now
An open source Mini SoC Generator which will generate SoC based on parameters.
Language:Python0 0
Talha-Ahmed-1/SoC-Now-Verification
Language:Verilog2
Talha-Ahmed-1/SoCoPy
SoC in Python
Language:Python2
Talha-Ahmed-1/SpM-Analysis
Language:C
Talha-Ahmed-1/symbiflow-magic
This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
Language:Makefile0 0
Talha-Ahmed-1/Talha-Ahmed-1
Language:JavaScript
Talha-Ahmed-1/timer
Chisel implementation of timer which has generic interface and we can connect it with any SoC using jigsaw framework.
Language:C++1
Talha-Ahmed-1/tinytapeout_flop_regfile
FlipFlop Based 1R1W Register File for TinyTapeout MPW7 Shuttle.
Language:Verilog1
Talha-Ahmed-1/Unit-testing-BFS-algorithm
Language:Python