/OPENCL-FPGA-CU-REPLICATION

Primary LanguageC++

OPENCL-FPGA-CU-REPLICATION

Tecsar

This fork contains 4 parts.

  1. OpenCL codes of a subset of Xilinx SDAccel benchmark suite version 2017.4 deployed on the AWS EC2 Cloud Xilinx VU9P FPGA. For the original benchmark page along with datasets and libs, refer here.

  2. Optimised version of the above codes(kernel, host and makefile) using compute unit replication optimization run on the same FPGA platform.

  3. A Compute Unit replication tool based off Python developed for the project

  4. Xilinx FPGA based OpenCL codes ported to run on any GPU.

Citation

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License

Copyright (c) 2019, University of North Carolina at Charlotte All rights reserved. - see the LICENSE file for details.