Tharal-Pius

Pinned Repositories

biriscv
32-bit Superscalar RISC-V CPU
Language:Verilog0 0 00
bitcoin
Bitcoin Core integration/staging tree
Language:C++0 0 00
Bluespec
0 1 00
Bluespec_SV
Language:Bluespec0 1 00
Chandra_Mohan_Nagar_21-24-17
Language:Jupyter Notebook0 0 00
ECE1373_2016_hft_on_fpga
High Frequency Trading using Vivado HLS
Language:Verilog0 0 00
hardcaml
Hardcaml is an OCaml library for designing hardware.
Language:OCaml0 0 00
iverilog
Icarus Verilog
Language:C++0 0 00
luespec
0 1 00
Tharal-Pius
Config files for my GitHub profile.
Language:JavaScript0 1 00

Tharal-Pius's Repositories

Tharal-Pius/biriscv
32-bit Superscalar RISC-V CPU
Language:Verilog0 0 00
Tharal-Pius/bitcoin
Bitcoin Core integration/staging tree
Language:C++0 0 00
Tharal-Pius/Bluespec
0 1 00
Tharal-Pius/Bluespec_SV
Language:Bluespec0 1 00
Tharal-Pius/Chandra_Mohan_Nagar_21-24-17
Language:Jupyter Notebook0 0 00
Tharal-Pius/ECE1373_2016_hft_on_fpga
High Frequency Trading using Vivado HLS
Language:Verilog0 0 00
Tharal-Pius/hardcaml
Hardcaml is an OCaml library for designing hardware.
Language:OCaml0 0 00
Tharal-Pius/iverilog
Icarus Verilog
Language:C++0 0 00
Tharal-Pius/luespec
0 1 00
Tharal-Pius/Tharal-Pius
Config files for my GitHub profile.
Language:JavaScript0 1 00
Tharal-Pius/MIPS_RISC
1 0
Tharal-Pius/riscv
RISC-V CPU Core (RV32IM)
Language:Verilog0 0
Tharal-Pius/Some-General-RTL-modules
Language:Verilog1 0
Tharal-Pius/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Language:SystemVerilog0 0
Tharal-Pius/verilog-pcie
Verilog PCI express components
Language:Verilog0 0
Tharal-Pius/VHDL
1 0
Tharal-Pius/Welcome-to-Open-Source
Make your first PR request! And enter the world of Open Source Contributions 🍉
0 0