/ECE475_lab6

Primary LanguageVHDL

ECE475_lab6

Development

Getting set up

  1. clone the repo
  2. open modelsim
  3. File -> new project
  4. Select the repo for project folder and name it whatever you want
  5. It will prompt you to add existing files. Add the .vhd files.
  6. Now in the project window select the VHDL files and make sure the disable optization is check in compiler options
  7. Right click and hit compile.

Testing

  1. In the library view double click work -> testbench. This will start a simulation
  2. Execute macro: Tools -> tcl -> execute macro
  3. select .do file that you want to run.

Contrubiting

  • Don't be a jerk.
  • Share your changes. We are share our changes with you.

TODO

  • Make Testbench
  • fill in architeture