/fsk-hamming-system

Primary LanguageVerilog

chisel-empty

usage

The files are in src/main/scala/<package_name> and src/test/scala/<package_name> separately. Change the package name to your own.

generate:

$ make

simulate:

$ make test

generate the verilog code into a certain directory:

// xx.scala
object AddMain extends App {
  println("Generating the adder hardware")
  emitVerilog(new Add(), Array("--target-dir", "generated"))
}

simple test (w/o print):

  "Add" should "work" in {
    test(new Add) { dut =>
      for (a <- 0 to 2) {
        for (b <- 0 to 3) {
          val result = a + b
          dut.io.a.poke(a.U)
          dut.io.b.poke(b.U)
          dut.clock.step(1)
          println(s"expect: $a + $b = $result")
          println(s"result: ${dut.io.c.peek()}")
          dut.io.c.expect(result.U)
        }
      }
    }
  }

simple test (w print):

// ...
println(s"expect: $a + $b = $result") // use scala
println(s"result: ${dut.io.c.peek()}") // extract from chisel
// ...

test with .vcd output:

test(new Add).withAnnotations(Seq(WriteVcdAnnotation))
// ...

then the vcd file can be viewed in test_run_dir:

vcd.png