TinyTapeout/tt06-verilog-template

Submission template for Tiny Tapeout 6 - Verilog HDL Projects

Tiny Tapeout Verilog Project Template

• Read the documentation for project

What is Tiny Tapeout?

TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Verilog Projects

1. Add your Verilog files to the src folder.
2. Edit the info.yaml and update information about your project, paying special attention to the source_files and top_module properties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool.
3. Edit docs/info.md and add a description of your project.
4. Optionally, add a testbench to the test folder. See test/README.md for more information.

The GitHub action will automatically build the ASIC files using OpenLane.

Enable GitHub actions to build the results page

• Enabling GitHub Pages

Resources

• FAQ
• Digital design lessons
• Learn how semiconductors work
• Join the community
• Build your design locally

What next?

• Submit your design to the next shuttle.
• Edit this README and explain your design, how it works, and how to test it.
• Share your project on your social network of choice:
  • LinkedIn #tinytapeout @TinyTapeout
  • Mastodon #tinytapeout @matthewvenn
  • X (formerly Twitter) #tinytapeout @matthewvenn