TommyWu-fdgkhdkgh

TommyWu-fdgkhdkgh's Stars

• conda-forge/miniforge

  A conda-forge distribution.

  Language:Shell6.8k342

• sparcians/map

  Modeling Architectural Platform

  Language:C++17161

• riscv-software-src/riscv-perf-model

  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

  Language:C++14461

• MIPS/esesc

  ESESC: A Fast Multicore Simulator

  Language:C83

• Minres/SystemC-Components

  A SystemC productivity library: https://minres.github.io/SystemC-Components/

  Language:JavaScript10127

• n-kremeris/verilator_basics

  Language:C++526

• P1umer/AFLplusplus-Extractor

  Language:C313

• jmpoep/vmprotect-3.5.1

  Language:C++1.9k1.2k

• aut0/vcml-nvdla

  VCML integration of Nvidia's NVDLA SystemC model

  Language:C++85

• ianrbuck/mp3-to-mp4

  An ffmpeg script for creating an MP4 video using a given MP3 as the audio and a given image as the video.

  Language:Batchfile73

• com-lihaoyi/mill

  Mill is a fast JVM build tool that supports Java, Scala and Kotlin. 2-4x faster than Gradle and 4-10x faster than Maven for common workflows, Mill aims to make your project’s build process performant, maintainable, and flexible

  Language:Scala2.3k364

• chipsalliance/rocket-tools

  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

  Language:Shell5358

• Affanmir/-single-cycle-RISC-V-processor-Verilog-

  Language:Verilog2

• leros-dev/leros

  A Tiny Processor Core

  Language:VHDL10319

• schoeberl/chisel-book

  Digital Design with Chisel

  Language:TeX784144

• ucb-bar/chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:Scala1.7k665

• deanwampler/programming-scala-book-code-examples

  The code examples used in Programming Scala, 2nd and 3rd Editions (O'Reilly)

  Language:Scala650412

• sanketny8/Processor_32bit_RISC_verilog

  Single cycle processor in verilog.

  Language:Verilog83

• ekiwi/rtl-fuzz-lab

  A Modular Open-Source Hardware Fuzzing Framework

  Language:SystemVerilog293

• ekiwi/rfuzz

  rfuzz: coverage-directed fuzzing for RTL research platform

  Language:Rust10013

• sysprog21/ca2023-lab3

  Lab3: Construct a single-cycle CPU with Chisel

  Language:Scala1853

• carlosedp/chiselv

  A RISC-V Core (RV32I) written in Chisel HDL

  Language:Scala9817

• martinKindall/risc-v-single-cycle

  A Single Cycle Risc-V 32 bit CPU

  Language:SystemVerilog362

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.6k249

• merledu/SIngle-Cycle-RISC-V-In-Verilog

  This repository contains the verilog code files of Single Cycle RISC-V architecture

  Language:Verilog206

• Sea-n/NCTU-109B-Comp-Org

  NCTU 109 Spring - Computer Organization

  Language:Verilog31

• HsuChiChen/ncku-computer-organization

  assembly code, RISC-V, and some implementation regarding computer organization

  Language:Verilog3

• SonalPinto/kronos

  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

  Language:SystemVerilog709

• Charlie5DH/RISC-V-Single-Cycle-uP

  Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture

  Language:VHDL111

• explcre/21Summer-VE370-Intro-to-Computer-Organization-Projects

  21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

  Language:Verilog10