TommyWu-fdgkhdkgh

TommyWu-fdgkhdkgh's Stars

• explcre/21Summer-VE370-Intro-to-Computer-Organization-Projects

  21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

  Language:Verilog10

• jerrylioon/Solutions-to-HDLbits-Verilog-sets

  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

  Language:Verilog8228

• ventanamicro/qemu

  Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

  Language:C22

• rick-heig/devmem2

  devmem2 - simple program to read/write from/to any location in memory.

  Language:C2

• ttdennis/fpicker

  fpicker is a Frida-based fuzzing suite supporting various modes (including AFL++ in-process fuzzing)

  Language:C26828

• ctf-wiki/ctf-wiki

  Come and join us, we need you!

  Language:Python8.4k1.4k

• sifive/meta-sifive

  SiFive OpenEmbedded / Yocto BSP Layer

  Language:BitBake5139

• rhysd/riscv32-cpu-chisel

  Learning how to make RISC-V 32bit CPU with Chisel

  Language:Scala634

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.3k1.1k

• chadyuu/riscv-chisel-book

  Language:Scala22041

• shioyadan/Konata

  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

  Language:JavaScript41538

• zeromq/czmq

  High-level C binding for ØMQ

  Language:C1.2k525

• zeromq/libzmq

  ZeroMQ core engine in C++, implements ZMTP/3.1

  Language:C++9.9k2.4k

• SudeepJoshi22/Minor-Project-2023-RISC-V-processor

  Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework.

  Language:Verilog101

• machineware-gmbh/mwr

  A library with commonly needed types and utlities

  Language:C++56

• Arteris-IP/tlm2-interfaces

  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols

  Language:C++5310

• openrisc/or1ksim

  The OpenRISC 1000 architectural simulator

  Language:C7243

• ics-jku/GUI-VP

  GUI-VP is a greatly extended and improved open-source RISC-V VP that enables the simulation of interactive graphical Linux applications.

  Language:C++101

• ics-jku/GUI-VP_Kit

  Quick-to-create and easy-to-use platform for experimentation with Linux on the open-source SystemC RISC-V based virtual prototype GUI-VP

  Language:Makefile71

• rems-project/sail

  Sail architecture definition language

  Language:Isabelle656122

• riscv/sail-riscv

  Sail RISC-V model

  Language:Coq490173

• agra-uni-bremen/riscv-vp

  RISC-V Virtual Prototype

  Language:C++15050

• Minres/HIFIVE1-VP

  A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS

  Language:C++115

• riscv-ovpsim/imperas-riscv-tests

  Language:C16638

• riscv-admin/riscv-ovpsim

  607

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.4k563

• riscv-software-src/riscv-pk

  RISC-V Proxy Kernel

  Language:C603312

• kenjihiranabe/The-Art-of-Linear-Algebra

  Graphic notes on Gilbert Strang's "Linear Algebra for Everyone"

  Language:PostScript18.4k2.2k

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl887199

• edgarigl/linux

  Linux kernel source tree

  Language:C11